From 7754ef7204e873aa33d55ebe5002257e3941e942 Mon Sep 17 00:00:00 2001 From: Bernhard Guillon Date: Sun, 22 Dec 2024 20:12:21 +0100 Subject: Import bk_ble from elektroda forum https://www.elektroda.com/rtvforum/topic3989434.html\#20742145 --- usr/ble_tst/src/stubs/re_stubs.S | 55 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 usr/ble_tst/src/stubs/re_stubs.S (limited to 'usr/ble_tst/src/stubs/re_stubs.S') diff --git a/usr/ble_tst/src/stubs/re_stubs.S b/usr/ble_tst/src/stubs/re_stubs.S new file mode 100644 index 0000000..774a390 --- /dev/null +++ b/usr/ble_tst/src/stubs/re_stubs.S @@ -0,0 +1,55 @@ + .thumb + .globl rwble_reset + .thumb_func + +rwble_reset: + push {r3, r4, r5, lr} + bl portDISABLE_FIQ + add r5, r0, #0 + bl portDISABLE_IRQ + movs r2, #128 // 0x80 + add r4, r0, #0 + ldr r3, BLE_BASETIMECNT_ADDR + lsl r2, r2, #24 + str r2, [r3, #0] +2: + ldr r2, [r3, #0] + cmp r2, #0 + blt 2b + ldr r2, BLE_FINETIMECNT_ADDR + ldr r3, BLE_BASETIMECNT_ADDR + ldr r3, [r3, #0] + ldr r0, [r2, #0] + add r0, r0, r3 + ldr r3, BLE_BDADDRL_ADDR + ldr r3, [r3, #0] + add r0, r0, r3 + bl srand + bl lld_core_reset + movs r0, #1 + bl lld_init + movs r0, #1 + bl lld_adv_test_init + bl llc_reset + movs r0, #1 + bl llm_init + bl em_buf_init + cmp r5, #0 + bne 0f + bl portENABLE_FIQ +0: + cmp r4, #0 + bne 1f + bl portENABLE_IRQ +1: + pop {r3, r4, r5, pc} + + .balign 4 + +BLE_BASETIMECNT_ADDR: + .word 0x0081001c // BLE_BASETIMECNT_ADDR +BLE_FINETIMECNT_ADDR: + .word 0x00810020 // BLE_FINETIMECNT_ADDR +BLE_BDADDRL_ADDR: + .word 0x00810024 // BLE_BDADDRL_ADDR + -- cgit v1.2.3